GitHub - Gladdy/numerical-fpga-thesis: Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH

The sample projects should work for Quartus 14.* and 15.0 The images have been compiled for a Cyclone V SX SoC—5CSXFC6D6F31C6N, obtained from here In order to get it working on a different SoC which supports the lightweight Avalon bridge interface, you'd have to regenerate the IO VHDL module. This can be done by loading the memory_io.qsys in Quartus' QSys system and generating the new bridge files