Apple's M1 Pro, M1 Max SoCs Investigated: New Performance and Efficiency Heights Last week, Apple had unveiled their new generation MacBook Pro laptop series, a new range of flagship devices that bring with them significant updates to the company’s professional and power-user oriented user-base. The new devices particularly differentiate themselves in that they’re now powered by two new additional

Apple Announces M1 Pro & M1 Max: Giant New Arm SoCs with All-Out Performance Today’s Apple Mac keynote has been very eventful, with the company announcing a new line-up of MacBook Pro devices, powered by two different new SoCs in Apple’s Silicon line-up: the new M1 Pro and the M1 Max. The M1 Pro and Max both follow-up on last year’s M1, Apple’s first generation Mac silicon that ushered in the begi

At Hot Chips last week, IBM announced its new mainframe Z processor. It’s a big interesting piece of kit that I want to do a wider piece on at some point, but there was one feature of that core design that I want to pluck out and focus on specifically. IBM Z is known for having big L3 caches, backed with a separate global L4 cache chip that operates as a cache between multiple sockets of processor

Interposers. EMIB. Foveros. Die-to-die stacking. ODI. AIB. TSVs. All these words and acronyms have one overriding feature – they are all involved in how two bits of silicon physically connect to each other. At the simple level, two chips can be connected through the printed circuit board – this is cheap but doesn’t allow for great bandwidth. Above this simple implementation, there are a variety of

SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP In the last few year’s we’ve seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we’ve seen a lot of vendors make the switch from licensing Arm’s architecture and IP designs to the open-source RISC-V architecture and either licensed or custom-made IP based on

The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU For the past eighteen months, Intel has paraded its new ‘Lakefield’ processor design around the press and the public as a paragon of new processor innovation. Inside, Intel pairs one of its fast peak performance cores with four of its lower power efficient cores, and uses novel technology in order to build the process

Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence 2019 was a great year for Arm. On the mobile side of things one could say it was business as usual, as the company continued to see successes with its Cortex cores, particularly the new Cortex-A77 which we’ve now seen employed in flagship chipsets such as the Snapdragon 865. The bigger news for the comp

AnandTech has reviewed these products as part of a paid partnership with Qualcomm. The contents of this article are entirely independent and solely reflect the editorial opinion of AnandTech. Over the last few years we’ve seen a lot of changes in the mobile market when it comes to the internal hardware of devices. At the heart of every smartphones sits the SoC, which dictates almost every aspect o

Kevin G - Thursday, September 15, 2016 - link Same here. I'm really curious about the differences between the four different dies IBM will be offering. Certainly the mix of two core types and IO types should fill the assorted niches found in the server market. rahvin - Thursday, September 15, 2016 - link I can wait, it will be a market share failure like every other power because IBM will price it

jardows2 - Thursday, July 21, 2016 - link Agreed. There are plenty of places you can go to find out how pretty your games will look, but this sort of stuff is much more interesting to me! Looking forward to the application numbers. Power8 may shape up to be a nice server alternative. I would like to see about virtualization. With the threaded capabilities, it might just be a good platform for that