Algorithms for Modern Hardware - Algorithmica
This is an upcoming high performance computing book titled “Algorithms for Modern Hardware” by Sergey Slotin. Its intended audience is everyone from performance engineers and practical algorithm researchers to undergraduate computer science students who have just finished an advanced algorithms course and want to learn more practical ways to speed up a program than by going from $O(n \log n)$ to $
Cache replacement policies - Wikipedia
This article is about general cache algorithms. For detailed algorithms specific to paging, see page replacement algorithm. For detailed algorithms specific to the cache between a CPU and RAM, see CPU cache. In computing, cache replacement policies (also known as cache replacement algorithms or cache algorithms) are optimizing instructions or algorithms which a computer program or hardware-maintai
Binary Search *eliminates* Branch Mispredictions
Searching in a short, sorted vector is a fairly common task. Lots of time, data sets are just small enough that it’s quicker (and simpler) to store them in a sorted vector than to use an alternative with asymptotically faster insertions. Even when we do use more complex data structures, it often makes sense to specialise the leaves and pack more data in a single node. How should we implement such
Fast Intersection of Sorted Lists Using SSE Instructions
Intersection of sorted lists is a cornerstone operation in many applications including search engines and databases because indexes are often implemented using different types of sorted structures. At GridDynamics, we recently worked on a custom database for realtime web analytics where fast intersection of very large lists of IDs was a must for good performance. From a functional point of view, w
Lock-Free Algorithms For Ultimate Performance
Sustainable Security Requirements with the ASVS Josh Grossman provides a brief overview of what the ASVS is, but takes a closer look at balancing trade-offs and prioritizing different security requirements. Josh shares how to make the process repeatable and how to implement it as part of your own organization's requirements process.
Explicit Multi-Threading (XMT) - Home Page
Explicit Multi-Threading (XMT): A PRAM-On-Chip Vision A Desktop Supercomputer For the prior version of this page that includes numerous links (some broken/expired) to news coverage click here . Summary In the past, mainstream computers used a single processor core. Nearly a decade ago all mainstream commercial computers switched to using multiple cores (due to technical reasons, such as overheatin
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Speed up Sort in Peloton using AVX2 by xhad1234
Breaking the Multicore Bottleneck
https://client.blueskybroadcast.com/SIAM12/PP/PDF/Yelick_IP7_2-17-12_1-30pm.pdf