Verilog - $readmemhと$readmemb//テストベンチ module testbench; reg CLK; reg RST; wire [11:0] ADDR; wire [31:0] XDATA; DUMMY_ROM DUMMY_ROM( .CLK(CLK), .RST(RST), .ADDR(ADDR), .XDATA(XDATA) ); DUMMY_ADDR DUMMY_ADDR( .CLK(CLK), .RST(RST), .XADDR(ADDR) ); parameter STEP = 10; always #(STEP / 2) CLK = ~CLK; initial begin $dumpfile("wave.vcd"); $dumpvars(0, testbench); $monitor ("%t: CLK = %b, RST = %b , ADDR = %h, XDATA = %h", $time, CLK
