"UCore is a RISC microprocessor compatible of the MIPS32R2 Instruction Set. It can run all the MIPS32R2 instructions except the branch likely instructions. For these instructions are not recommended in the specification. "

masterq のブックマーク 2013/02/13 13:26

<blockquote class="hatena-bookmark-comment"><a class="comment-info" href="https://b.hatena.ne.jp/entry/132540774/comment/masterq" data-user-id="masterq" data-entry-url="https://b.hatena.ne.jp/entry/s/opencores.org/projects/ucore" data-original-href="https://opencores.org/projects/ucore" data-entry-favicon="https://cdn-ak2.favicon.st-hatena.com/64?url=https%3A%2F%2Fopencores.org%2Fprojects%2Fucore" data-user-icon="/users/masterq/profile.png">Overview :: UCore :: OpenCores</a><ul class="comment-tag" style="list-style: none; margin: 0px;"><li style="float: left">[<a href="https://b.hatena.ne.jp/q/fpga">fpga</a>]</li><li style="float: left">[<a href="https://b.hatena.ne.jp/q/mips">mips</a>]</li><li style="float: left">[<a href="https://b.hatena.ne.jp/q/mmu">mmu</a>]</li><li style="float: left">[<a href="https://b.hatena.ne.jp/q/cpu">cpu</a>]</li></ul><br><p style="clear: left">&quot;UCore is a RISC microprocessor compatible of the MIPS32R2 Instruction Set. It can run all the MIPS32R2 instructions except the branch likely instructions. For these instructions are not recommended in the specification. &quot;</p><a class="datetime" href="https://b.hatena.ne.jp/masterq/20130213#bookmark-132540774"><span class="datetime-body">2013/02/13 13:26</span></a></blockquote><script src="https://b.st-hatena.com/js/comment-widget.js" charset="utf-8" async></script>

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