CPU Cache Essentials
This post came to my mind after watching the excellent presentation of Scott Meyers called "CPU Caches and Why You care". This post will try to summarize the ideas of the presentation so if you have some spare time you can just watch the presentation on video. To emphasize importance of cpu caches in our daily work we start with 2 examples: The first problem is a simple traversing of 2 dimensional
InsightfulLogic
Caching In: Understand, Measure and Use your CPU Cache more effectively Slides from my Javaone talk on CPU Caching Wed 02 October 2013 I've put the slides online for Javaone talk on CPU Cache Optimisation. Here's the talk abstract: Modern computationally intensive tasks are rarely bottlenecked by the absolute performance of your processor cores. The real bottleneck in 2013 is getting data out of m
仮想メモリーを支えるもうひとつのキャッシュ TLB (1/3)
仮想アドレスと物理アドレスを変換する Address Translationの基本 前回はメモリーの階層構造と同様に、複数段階のキャッシュ構成があることを説明した。今回はちょっと見方を変えた話をしたい。まず、キャッシュという形でCPU内部に搭載されている、別のメモリーについて触れよう。 ご存知の通り、1次キャッシュは通常「ハーバード・アーキテクチャー」と呼ばれる構造に基づき、命令用とデータ用がそれぞれ別に用意される。詳細は後述するが、2次キャッシュや最近では3次キャッシュを搭載するプロセッサーも多くなった。ただ、これらはいずれも「プログラムそのもの、およびプログラムの実行時に利用されるデータ」である。 「ではそれ以外に何かあるのか？」と言われると、これが結構ある。一番多く利用されるのが「TLB」(Translation Lookaside Buffer)と言われるものだ。これは「仮想記憶」
CPU Cache Flushing Fallacy
Even from highly experienced technologists I often hear talk about how certain operations cause a CPU cache to "flush". This seems to be illustrating a very common fallacy about how CPU caches work, and how the cache sub-system interacts with the execution cores. In this article I will attempt to explain the function CPU caches fulfil, and how the cores, which execute our programs of instruction
Big List of 20 Common Bottlenecks - High Scalability -
Hey guys - it's always awesome to see a listing of common bottlenecks, especially if you are new to some technology or environments. But it's also dangerous to use such a list as a crutch - or a replacement - to really being able to understand performance bottleneck root cause and resource utilization. http://mtomlins.blogspot.com/2012/04/bucket-full-of-bottlenecks.html Cheers, -mt Nice list, have
Memory Access Patterns Are Important
In high-performance computing it is often said that the cost of a cache-miss is the largest performance penalty for an algorithm. For many years the increase in speed of our processors has greatly outstripped latency gains to main-memory. Bandwidth to main-memory has greatly increased via wider, and multi-channel, buses however the latency has not significantly reduced. To hide this latency our
How long does it take to make a context switch?
That's a interesting question I'm willing to spend some of my time on. Someone at StumbleUpon emitted the hypothesis that with all the improvements in the Nehalem architecture (marketed as Intel i7), context switching would be much faster. How would you devise a test to empirically find an answer to this question? How expensive are context switches anyway? (tl;dr answer: very expensive) The lineup
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Intel Xeonにおけるメモリレイテンシの測定についての表示 - memory profiling tool - OSDN
https://www.akkadia.org/drepper/summit08-memperf.pdf