GitHub - Wren6991/Hazard3: 3-stage RV32IMACZb* processor with debugHazard3 is a 3-stage RISC-V processor, implementing the RV32I instruction set and the following optional extensions: M: integer multiply/divide/modulo A : atomic memory operations, with AHB5 global exclusives C: compressed instructions Zicsr: CSR access Zba: address generation Zbb: basic bit manipulation Zbc: carry-less multiplication Zbs: single-bit manipulation Zbkb: basic bit manipulation for s
GitHub - AleksandarKostovic/Riscy-SoC: Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
