GitHub - darklife/darkriscv: opensouce RISC-V cpu core implemented in Verilog from scratch in one night!Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the DarkRISCV softcore started as an proof of concept for the opensource RISC-V instruction set. Although the code is small and crude when compared with other RISC-V implementations, the DarkRISCV has lots of impressive features: implements the UCB RISC-V RV32E and RV32I user space instruction set optional CSRs for interrupts and debu
