GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementationThis repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs : RV32I[M][A][F[D]][C] instruction set Pipelined from 2 to 5+ stages ([Fetch*X], Decode, Execute, [Memory], [WriteBack]) 1.44 DMIPS/MHz --no-inline when nearly all features are enabled (1.57 DMIPS/MHz when the divider lookup table is enabled) Optimized for FPGA, does not use any vendor specific IP block / primi
