https://www.youtube.com/channel/UC1kyKOb_sv52OfVTZW5WXPg
J1a SwapForth built with IceStorm
J1a SwapForth built with IceStorm Project IceStorm aims to reverse engineer some Lattice FPGAs, and provides a working tool chain for synthesizing designs and downloading them into the hardware. The J1a CPU is a minimal 16-bit Verilog CPU, fits easily on the Lattice HX20-1K on the Lattice iCEstick evaluation board. After some help from the people at project IceStorm, it is now buildable using the
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icebox_vlog(1) — fpga-icestorm — Debian testing — Debian Manpages
GitHub - AleksandarKostovic/Riscy-SoC: Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
GitHub - alangarf/apple-one: An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
YosysHQ SBY documentation
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PlatformIO Registry
http://www.clifford.at/papers/2015/icestorm-flow/slides-fosdem16.pdf
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GitHub - laanwj/yosys-ice-experiments: Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain
GitHub - nesl/ice40_examples: Public examples of ICE40 HX8K examples using Icestorm
GitHub - peepo/verilog_tutorials_BB: verilog tutorials for iCE40HX8K Breakout Board
GitHub - FPGAwars/apio: :seedling: Open source ecosystem for open FPGA boards
GitHub - ddm/icestick-verilog-tutorial: Verilog example for the iCEstick Evaluation Kit using icestorm, arachne-pnr, yosys and iverilog
GitHub - OLIMEX/iCE40HX1K-EVB: FPGA development board made with KiCAD
GitHub - Obijuan/open-fpga-verilog-tutorial: Learn how to design digital systems and synthesize them into an FPGA using only opensource tools