GitHub - SpinalHDL/SpinalHDL: Scala based HDL
SpinalHDL is: A language to describe digital hardware Compatible with EDA tools, as it generates VHDL/Verilog files Much more powerful than VHDL, Verilog, and SystemVerilog in its syntax and features Much less verbose than VHDL, Verilog, and SystemVerilog Not an HLS, nor based on the event-driven paradigm Only generates what you asked it in a one-to-one way (no black-magic, no black box) Not intro
Chisel: Constructing Hardware in an Scala Embedded Language
ScalaChisel is powered by Scala and brings all the power of object-oriented and functional programming to type-safe hardware design and generation. Chisel, the Chisel standard library, and Chisel testing infrastructure enable agile, expressive, and reusable hardware design methodologies. FIRRTLThe FIRRTL circuit compiler starts after Chisel and enables backend (FPGA, ASIC, technology) specializati
Synthesijer
THIS SITE IS NO LONGER ACTIVELY MAINTAINED, FOR RECENT RELEASES, PLEASE REFER TO: http://synthesijer.github.io/web/. About Synthesijer Download Quick Start Samples Resources ChangeLog License About Synthesijer Synthesijer is a high-level synthesis tool, which generates VHDL and Verilog HDL code from Java code. Synthesijer also provides a backend to generate VHDL/Verilog HDL, which helps to develop
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