Tensor Processing Unit - Wikipedia
First generation TPU[edit] The first-generation TPU is an 8-bit matrix multiplication engine, driven with CISC instructions by the host processor across a PCIe 3.0 bus. It is manufactured on a 28 nm process with a die size ≤ 331 mm2. The clock speed is 700 MHz and it has a thermal design power of 28–40 W. It has 28 MiB of on chip memory, and 4 MiB of 32-bit accumulators taking the results of a 256
Meet the 69-year-old professor who left retirement to help lead one of Google's most crucial projects
Professor David Patterson retired from U.C. Berkeley last summer after a 40-year academic career in computer architecture.He's now a key part of the team behind a critical chip that Google uses for artificial intelligence processing.Without this chip, Google top execs estimated it would have had to double its data centers to support even a limited amount of voice processing. A year ago the Univers
Tensor Processing Unit: Google's LSI designed for neural network - builderscon tokyo 2017
Tensor Processing Unit: Google's LSI designed for neural network accepted Abstract This session takes a detailed look at the architecture of Google’s Tensor Processing Unit (TPU), the LSI designed for neural network processing. We’ll cover quantization, CISC design, as well as the systolic array matrix unit that is the heart of the device. You’ll learn how a minimalistic design philosophy and a ti
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