GitHub - olofk/serv: SERV - The SErial RISC-V CPUYou signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session. You switched accounts on another tab or window. Reload to refresh your session. Dismiss alert
J1a SwapForth built with IceStorm
J1a SwapForth built with IceStorm Project IceStorm aims to reverse engineer some Lattice FPGAs, and provides a working tool chain for synthesizing designs and downloading them into the hardware. The J1a CPU is a minimal 16-bit Verilog CPU, fits easily on the Lattice HX20-1K on the Lattice iCEstick evaluation board. After some help from the people at project IceStorm, it is now buildable using the
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icebox_vlog(1) — fpga-icestorm — Debian testing — Debian Manpages
iCE40 FPGA Toolchain on Linux
icestorm/examples/icestick/rs232demo.v at master · YosysHQ/icestorm
GitHub - grahamedgecombe/icicle: 32-bit RISC-V system on chip for iCE40 FPGAs
GitHub - FPGAwars/apio: :seedling: Open source ecosystem for open FPGA boards
