GitHub - Wren6991/Hazard3: 3-stage RV32IMACZb* processor with debug
Hazard3 is a 3-stage RISC-V processor, implementing the RV32I instruction set and the following optional extensions: M: integer multiply/divide/modulo A : atomic memory operations, with AHB5 global exclusives C: compressed instructions Zicsr: CSR access Zba: address generation Zbb: basic bit manipulation Zbc: carry-less multiplication Zbs: single-bit manipulation Zbkb: basic bit manipulation for s
GitHub - VectorBlox/orca: RISC-V by VectorBlox
Vectorblox ORCA ORCA is an implementation of RISC-V. It is intended to target FPGAs and can be configured as either RV32I a RV32IM core. ORCA can be used as a standalone processor, but was built to be a host to Vectorblox's proprietary Lightweight Vector Extensions (LVE) or full-fledged Matrix processor MXP. It has optional AXI3/4 instruction and data caches, a separate AXI4-Lite interface for unc
Chisel: Constructing Hardware in an Scala Embedded Language
ScalaChisel is powered by Scala and brings all the power of object-oriented and functional programming to type-safe hardware design and generation. Chisel, the Chisel standard library, and Chisel testing infrastructure enable agile, expressive, and reusable hardware design methodologies. FIRRTLThe FIRRTL circuit compiler starts after Chisel and enables backend (FPGA, ASIC, technology) specializati
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