10. 10 VHDLによるRTL設計の例 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity led is port ( clk, reset : in std_logic; q : out std_logic ); end led; architecture RTL of led is signal c : unsigned(31 downto 0); begin q <= c(5); process(clk) begin if clk'event and clk = '1' then if reset = '1' then c <= (others => '0'); else c <= c + 1; end if; end if; end process; end RTL; カウンタの