MVSIS: Logic Synthesis and Verification
overview The MVSIS group at Berkeley studies logic synthesis and verification for VLSI design. The main focus is on new optimization algorithms that improve the quality of circuits generated by automatic synthesis tools and, at the same time, are scalable for practical use. history Most of the algorithms developed by our group are incorporated in an open-source program called MVSIS which is the su
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Handshake Synchronizer Design and Verilog Code
http://www.ee.ic.ac.uk/pcheung/publications/FPL%20Royal%26Cheung.pdf
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CSDL | IEEE Computer Society
Assertion-Based Design
