Verilog-mode - Intro - Veripool

Verilog-Mode: Reducing the Veri-Tedium Minor updates 2008-09-01 Wilson Snyder wsnyder@wsnyder.org SNUG San Jose 2001 Abstract The Verilog Language has several design deficiencies which force users to enter and maintain redundant information, such as argument lists, sensitivity lists, and cross-module wire statements. Supporting this information leads to potential errors, lack of maintainability, a