サクサク読めて、アプリ限定の機能も多数!
トップへ戻る
災害への備え
research.cs.wisc.edu
Hardware Support for NVM Programming 1 • Ordering • Transactions • Write endurance Outline 2 Volatile Memory Ordering • Write-back caching – Improves performance – Reorders writes to DRAM • Reordering to DRAM does not break correctness • Memory consistency orders stores between CPUs CPU Write-back Cache DRAM B A B A STORE A STORE B CPU 3 • Recovery depends on write ordering CPU Write-back Cache NV
Shore - A High-Performance, Scalable, Persistent Object Repository The publicly-available SHORE Storage Manager has been replaced by SHORE-MT. Please see its home page here . Document Contents: Objective Status Overview Release Information Mailing Lists Documentation about the current storage-manager-only release (2.0) Source and Documentation available by FTP. Overview : slides from a short prese
このページを最初にブックマークしてみませんか?
『research.cs.wisc.edu』の新着エントリーを見る
j次のブックマーク
k前のブックマーク
lあとで読む
eコメント一覧を開く
oページを開く