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By: Linus Torvalds (torvalds.delete@this.linux-foundation.org), January 6, 2020 1:28 pm Gionatan Danti (g.danti.delete@this.assyoma.it) on January 6, 2020 12:13 pm wrote: > > However, I have a question about a recent kernel change that broke an important 3rd party > module: zfs. I don't want absolutely to flame, and feel free to not reply if think so. Note that "we don't break users" is literally

Linus Torvalds (torvalds.delete@this.linux-foundation.org) on January 3, 2020 7:05 pm wrote: > Beastian (no.email.delete@this.aol.com) on January 3, 2020 11:46 am wrote: > > I'm usually on the other side of these primitives when I write code as a consumer of them, > > but it's very interesting to read about the nuances related to their implementations: > > The whole post seems to be just wrong, an

Linus Torvalds (torvalds.delete@this.linux-foundation.org) on February 21, 2019 9:03 am wrote: > Michael S (already5chosen.delete@this.yahoo.com) on February 21, 2019 12:53 am wrote: > > > > Linus is the ultimate unixoid. I paid attention that even > > less devoted unixoids are high on native development. > > For me, as one that drinks and breaths cross-development all his professional > > life, i

Pages: 1 2 3 4 5 6 Over the last 5 years, high performance microprocessors have changed dramatically. One of the most significant influences is the increasing level of integration that is enabled by Moore’s Law. In the context of semiconductors, integration is an ever-present fact of life, reducing system power consumption and cost and increasing performance. The latest incarnation of this trend i

Pages: 1 2 3 4 5 In the early 1980’s, Reduced Instruction Set Computing (RISC) promised huge efficiencies to new instruction set architectures. In particular, the simpler ISAs enabled small teams to design very high performance processors, compared with existing complex instruction sets (collectively termed CISC). Within a short span of time, nearly a dozen RISC architectures were born, targeting

Pages: 1 2 3 4 Two of my personal areas of interest and expertise are speculative multithreading (SpMT) and transactional memory (or TM). Both are techniques designed to make multi-core processors and parallel programming more amenable to developers. For several years, I was the co-founder of Strandera, a start up that was developing speculative multithreading, based on transactional memory and dy

Pages: 1 2 3 4 5 6 7 8 9 10 Introduction Sandy Bridge was once known by the codename Gesher, meaning bridge in Hebrew. While most Intel codenames are geographic in nature, in this case, it can be interpreted as a rather apt metaphor. Sandy Bridge is a synthesis of three separate worlds within Intel – blending the microarchitectures of the Pentium Pro and the Pentium 4 and a new implementation of t

RWT on TwitterRT @TheKanter: Ashlee is a friend and an amazing writer! You won’t be disappointed with his book :) about 1 year agoSomeone loves our forums!!! https://t.co/4flSfwtEQr about 1 year ago@CRN_WMid I totally agree about importance of midwives, but did you know that this is the Twitter account of a tech… https://t.co/Kq3xbQMw4C about 2 years ago in reply to CRN_WMid

Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Coherency Leaps Forward at Intel CSI is a switched fabric and a natural fit for cache coherent non-uniform memory architectures (ccNUMA). However, simply recycling Intel’s existing MESI protocol and grafting it onto a ccNUMA system is far from efficient. The MESI protocol complements Intel’s older bus-based architecture and elegantly enforces coherency. But

Pages: 1 2 3 4 5 6 7 8 9 10 Introduction During the early part of the decade, the paths for Intel and AMD’s CPU architecture diverged rather remarkably. Intel focused on the Pentium 4, a high clock speed design that relied on proper coding practices by programmers to achieve high performance. AMD in contrast, focused on extending the K7 architecture by overhauling the system and memory interfaces